Patent · US Active

Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size

US8377820B2 · kind B2 · utility

3Cited by

2References

24Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Thomas Werner · Radebeul, DE
Kai Frohberg · Meißen, DE
Frank Feustel · Dresden, DE

Key dates

Filing date	Jan 25, 2010
Grant date	Feb 19, 2013
Priority date	—
Expiry date	Feb 7, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.