High endurance non-volatile memory cell and array
US8384147B2 · kind B2 · utility
4Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2011 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | May 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems of electrically programmable and erasable memory cell are disclosed. In one exemplary implementation, a cell may have two storage transistors in a substrate of semiconductor material of a first cooductivity type The first storage transistor is of the type having a first region and a second region each of a second conductivity type in the substrate The second storage transistor is of the type having a third region and a fourth region each of a second conductivity type in the substrate. Arrays formed of such memory cells and non-volatile memory cells are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.