Contact optimization for enhancing stress transfer in closely spaced transistors
US8384161B2 · kind B2 · utility
3Cited by
1References
26Claims
0Family size
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Key dates
| Filing date | Jun 25, 2010 |
| Grant date | Feb 26, 2013 |
| Priority date | — |
| Expiry date | Apr 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
By appropriately designing the geometric configuration of a contact level of a sophisticated semiconductor device, the tensile stress level of contact elements in N-channel transistors may be increased, while the tensile strain component of contact elements caused in the P-channel transistor may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.