Method for manufacturing chips
US8389327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2008 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Feb 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04941
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing chips (1, 2), in which at least one diaphragm (11, 12) is produced in the surface layer of a semiconductor substrate (10) spanning a cavity (13). The functionality of the chip (1, 2) is then integrated into the diaphragm (11, 12). In order to separate the chip (1, 2), the diaphragm (11, 12) is detached from the substrate composite. The method according to the present invention is characterized by metal plating of the back of the chip (1, 2) in an electroplating process before the chip is separated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.