p-FET with a strained nanowire channel and embedded SiGe source and drain stressors

US8399314B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Guy M. Cohen · Potsdam, US
• Conal E. Murray · Yorktown Heights, US
• Michael J. Rooks · Briarcliff Manor, US

Key dates

• Filing date: Mar 25, 2010
• Grant date: Mar 19, 2013
• Expiry date: Sep 23, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.