Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer
US8399336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2008 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | May 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.