Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

US8404550B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Thilo Scheiper · Dresden, DE
• Sven Beyer · Dresden, DE
• Andy Wei · Queensbury, US
• Jan Hoentschel · Dresden, DE

Key dates

• Filing date: Oct 15, 2010
• Grant date: Mar 26, 2013
• Expiry date: Jan 29, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.