Chip package with channel stiffener frame
US8405187B2 · kind B2 · utility
4Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2011 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jun 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.