Integrated circuit package system for package stacking and method of manufacture therefor
US8409920B2 · kind B2 · utility
10Cited by
27References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Jul 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package system and method of manufacture therefor includes: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.