SOI (silicon on insulator) structure semiconductor device and method of manufacturing the same
US8410573B2 · kind B2 · utility
1Cited by
9References
13Claims
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Key dates
| Filing date | Oct 20, 2008 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Jul 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.