Lead-free structures in a semiconductor device
US8410604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Jun 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor die and a plurality of lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes a plurality of metal layers and a plurality of dielectric layers. One of the metal layers includes a plurality of contact pads corresponding to the plurality of lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having a plurality of respective openings for the contact pad. A plurality of respective copper posts is disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the plurality of lead-free solder bumps and the plurality of copper posts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.