STI silicon nitride cap for flat FEOL topology

US8415214B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Frank Jakubowski · Dresden, DE
• Peter Baars · Dresden, DE
• Jorg Radecker · Dresden, DE

Key dates

• Filing date: Jan 20, 2011
• Grant date: Apr 9, 2013
• Expiry date: Mar 18, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Transistor devices are formed with a nitride cap over STI regions during FEOL processing. Embodiments include forming a pad oxide layer on a substrate, forming an STI region in the substrate so that the top surface is level with the top surface of the pad oxide, forming a nitride cap on the STI region and on a portion of the pad oxide layer on each side of the STI region, implanting a dopant into the substrate, deglazing the nitride cap and pad oxide layer, removing the nitride cap, and removing the pad oxide layer. Embodiments include forming a silicon germanium channel (c-SiGe) in the substrate prior to deglazing the pad oxide layer. The nitride cap protects the STI regions and immediately adjacent area during processes that tend to degrade the STI oxide, thereby providing a substantially divot free substrate and an STI region with a zero step height for the subsequently deposited high-k dielectric and metal electrode.