Methods for reducing loading effects during film formation
US8415236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jul 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.