Controlled localized defect paths for resistive memories
US8420478B2 · kind B2 · utility
15Cited by
13References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2009 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.