Non-volatile memory and method with post-write read and adaptive re-write to manage errors
US8423866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | May 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.