Method of forming stacked-die packages
US8426256B2 · kind B2 · utility
19Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2010 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Feb 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.