Method for growing strain-inducing materials in CMOS circuits in a gate first flow

US8426265B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• GlobalFoundries Inc. · KY

Inventors

• Bo Bai · Beijing, CN
• Linda Black · Wappingers Falls, US
• Abhishek Dube · Fishkill, US
• Judson R. Holt · Wappingers Falls, US
• Viorel Ontalus · Danbury, US
• Kathryn T. Schonenberg · Wappingers Falls, US
• Matthew W. Stoker · Poughkeepsie, US
• Keith H. Tabakman · Newburgh, US

Key dates

• Filing date: Nov 3, 2010
• Grant date: Apr 23, 2013
• Expiry date: Mar 16, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0172

Abstract

A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.