Back diffusion suppression structures
US8436398B2 · kind B2 · utility
15Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2010 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Nov 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.