Method for manufacturing multi-gate transistor device
US8440511B1 · kind B1 · utility
3Cited by
40References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2011 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Nov 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.