Method to form low series resistance transistor devices on silicon on insulator layer
US8440552B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2012 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Jan 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.