Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same
US8445356B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2012 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jan 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76289
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of forming a structure and a resulting structure. The method includes providing a semiconductor substrate; forming a first opening to a first depth in the semiconductor substrate; amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized semiconductor sidewalls in a lower portion of the first opening; enlarging only the lower portion of the first opening using an etch process that is selective to the unamorphized semiconductor sidewalls; filling the first opening with an insulator material to form a deep trench isolation (DTI) structure and implanting a first well region and a second well region into the semiconductor substrate. The first well and the second well are separated from one another by the enlarged lower portion of the first opening. In the structure sidewalls of a top portion of a DTI and sidewalls of an STI are formed of doped, re-crystallized silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.