Method of fabricating a sealing structure for high-k metal gate
US8450161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2012 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | May 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.