Integrated circuit package system with embedded die superstructure and method of manufacture thereof
US8455300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | May 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit package system includes: providing a through-silicon-via die having conductive vias therethrough; forming a first redistribution layer on a bottom of the through-silicon-via die coupled to the conductive vias; forming a second redistribution layer on the top of the through-silicon-via die coupled to the conductive vias; fabricating an embedded die superstructure on the second redistribution layer including: mounting an integrated circuit die to the second redistribution layer, forming a core material layer on the second redistribution layer to be coplanar with the integrated circuit die, forming a first build-up layer, having contact links coupled to the integrated circuit die, on the core material layer, and coupling component interconnect pads to the contact links; and forming system interconnects on the first redistribution layer for coupling the through-silicon-via die, the integrated circuit die, the component interconnect pads, or a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.