Non-volatile memory unit cell with improved sensing margin and reliability
US8456916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2012 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Jul 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.