Spacer and process to enhance the strain in the channel with stress liner

US8461009B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Atul Ajmera · Wappingers Falls, US
• Christopher V. Baiocco · Newburgh, US
• Xiangdong Chen · Irvine, US
• Wenzhi Gao · Singapore, SG
• Young Way Teh · Singapore, SG

Key dates

• Filing date: Feb 28, 2006
• Grant date: Jun 11, 2013
• Expiry date: Mar 17, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/015

Abstract

Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.