Ultrahigh density vertical NAND memory device and method of making thereof
US8461641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2012 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Nov 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
Monolithic three dimensional NAND string includes a semiconductor channel having a U-shaped pipe shape. A plurality of control gate electrodes having a strip shape extends substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. A cut area separates the plurality of control gate electrodes in a direction substantially perpendicular to the major surface of the substrate. A blocking dielectric is located in contact with the plurality of control gate electrodes, a charge storage region located in contact with the blocking dielectric and a tunnel dielectric is located between the charge storage region and the semiconductor channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.