Method of making strained silicon channel semiconductor structure
US8476169B2 · kind B2 · utility
3Cited by
76References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2011 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Oct 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.