Stress reduction in chip packaging by using a low-temperature chip-package connection regime

US8482123B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Michael Grillberger · Radebeul, DE
• Matthias Lehr · Dresden, DE
• Thomas Werner · Radebeul, DE

Key dates

• Filing date: Jul 11, 2011
• Grant date: Jul 9, 2013
• Expiry date: Aug 4, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.