Semiconductor constructions and methods of forming patterns
US8486611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2010 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Aug 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.