Low resistance source and drain extensions for ETSOI

US8486778B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Balasubramanian S. Haran · Watervliet, US
• Hemanth Jagannathan · Niskayuna, US
• Sivananda K. Kanakasabapathy · Niskayuna, US
• Sanjay C. Mehta · Niskayuna, US

Key dates

• Filing date: Jul 15, 2011
• Grant date: Jul 16, 2013
• Expiry date: Nov 16, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/015

Abstract

A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.