3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer

US8492869B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Mukta G. Farooq · Hopewell Junction, US
• Robert Hannon · Land O' Lakes, US
• Subramanian S. Iyer · Yorktown Heights, US
• Steven J. Koester · Toledo, US
• Fei Liu · Wuxi, CN
• Sampath Purushothaman · Yorktown Heights, US
• Albert M. Young · Fishkill, US
• Roy R. Yu · Poughkeepsie, US

Key dates

• Filing date: Aug 10, 2012
• Grant date: Jul 23, 2013
• Expiry date: Aug 10, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.