Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8502387B2 · kind B2 · utility
45Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Feb 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: forming an outer contact pad having an outer pad top side; mounting an integrated circuit above the outer pad top side; forming an encapsulation having an encapsulation top side and an encapsulation bottom side, the encapsulation over the integrated circuit with the encapsulation bottom side coplanar with the outer pad top side; and forming a vertical interconnect through the encapsulation, the vertical interconnect having an interconnect bottom side directly on the outer pad top side and an interconnect top side exposed from the encapsulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.