Inventor · Suneung-ri, KR

KyuWon Lee

18Patents

6h-index

21Co-inventors

62Inventor score

Filing activity: May 30, 2008 → May 22, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8502387B2	Integrated circuit packaging system with vertical interconnection and method of manufacture thereof	Electricity	45	Active
US8004093B2	Integrated circuit package stacking system	Electricity	35	Active
US7683469B2	Package-on-package system with heat spreader	Electricity	24	Active
US8519544B2	Semiconductor device and method of forming WLCSP structure using protruded MLP	Electricity	10	Active
US8531012B2	Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV	Electricity	9	Active
US8273604B2	Semiconductor device and method of forming WLCSP structure using protruded MLP	Electricity	7	Active
US8432028B2	Integrated circuit packaging system with package-on-package and method of manufacture thereof	Electricity	6	Active
US9401347B2	Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV	Electricity	5	Active
US8932908B2	Semiconductor device and method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die	Electricity	4	Active
US8574964B2	Semiconductor device and method of forming electrical interconnection between semiconductor die and substrate with continuous body of solder tape	Electricity	4	Active
US8310038B2	Integrated circuit packaging system with embedded conductive structure and method of manufacture thereof	Electricity	2	Active
US8288202B2	Method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die	Electricity	1	Active
US8937371B2	Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV	Electricity	1	Active
US8502392B2	Semiconductor device with partially-etched conductive layer recessed within substrate for bonding to semiconductor die	Electricity	0	Active
US9082887B1	Integrated circuit packaging system with posts and method of manufacture thereof	Electricity	0	Active
US11775729B2	Technology file process rule validation	Physics	0	Active
US11764136B2	Semiconductor device and method of forming bump pad array on substrate for ground connection for heat sink/shielding structure	Electricity	0	Active
US12211778B2	Semiconductor device and method of forming bump pad array on substrate for ground connection for heat sink/shielding structure	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.