Alignment tolerant semiconductor contact and method
US8507375B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2012 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Feb 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.