Read architecture for MRAM
US8509003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Nov 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.