Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates

US8513728B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Parviz Ghazavi · San Jose, US
• Hieu Van Tran · San Jose, US
• Shiuh-Luen Wang · San Jose, US
• Nhan Do · Saratoga, US
• Henry A. Om'Mani · Santa Clara, US

Key dates

• Filing date: Nov 17, 2011
• Grant date: Aug 20, 2013
• Expiry date: Dec 1, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.