Flexible interconnect pattern on semiconductor package
US8518750B2 · kind B2 · utility
0Cited by
19References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2013 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Jan 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.