Semiconductor structure and method for interconnection of integrated circuits
US8519528B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Sep 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an interposer resistant to warping is provided. The interposer includes a semiconductor body having a first contact array included on a first side of the semiconductor body. Vias are formed through the semiconductor body. One or more wiring layers are included on the first side of the semiconductor body. The wiring layers electrically couple each contact of the first contact array to a respective one of the vias. Contacts of a second contact array, included on a second side of the semiconductor body, are respectively coupled to the vias. A stabilization layer is included on the second side of the semiconductor body. The stabilization layer is configured to counteract stresses exerted on a front side of the interposer due to thermal expansion of wiring layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.