Reducing latency in serializer-deserializer links
US8527676B2 · kind B2 · utility
5Cited by
19References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 9, 2012 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | May 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.