Vertical silicide e-fuse
US8530319B2 · kind B2 · utility
4Cited by
27References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.