Method and system for minimizing carrier stress of a semiconductor device
US8531014B2 · kind B2 · utility
0Cited by
18References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Aug 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.