Technique for enhancing transistor performance by transistor specific contact design
US8541885B2 · kind B2 · utility
3Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2011 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Sep 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.