Integrated circuit packaging system with dielectric support and method of manufacture thereof
US8546957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2010 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having an outer pad at a substrate top side; forming a resist layer directly on the substrate top side, the resist layer having a resist top side with a channel array adjacent the outer pad exposed from the resist layer; mounting an integrated circuit having an active side facing the resist top side, the integrated circuit having a non-horizontal side adjacent the outer pad; and forming a dielectric between the active side and the resist top side, the dielectric having a fillet extended from the non-horizontal side to the substrate top side inside an inner extent of the channel array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.