Sidewall and chamfer protection during hard mask removal for interconnect patterning
US8551877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | May 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.