Integrated circuits having improved metal gate structures and methods for fabricating same
US8552505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Apr 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a PFET trench in a PFET region and an NFET trench in an NFET region of an interlayer dielectric material on a semiconductor surface. The NFET trench is partially filled with an N-type work function metal layer to define an inner cavity. The PFET trench and the inner cavity in the NFET trench are partially filled with a P-type work function metal layer to define a central void in each trench. In the method, the central voids are filled with a metal fill to form metal gate structures. A single recessing process is then performed to recess portions of each metal gate structure within each trench to form a recess in each trench above the respective metal gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.