Statistical clock cycle computation

US8560989B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Nathan C. Buck · Underhill, US
• Brian M. Dreibelbis · Underhill, US
• John P. Dubuque · Jericho, US
• Eric A. Foreman · Saint Albans, US
• James C. Gregerson · Hyde Park, US
• Peter A. Habitz · South Burlington, US
• Jeffrey G. Hemmett · South Burlington, US
• Debjit Sinha · Wappingers Falls, US
• Natesan Venkateswaran · Hopewell Junction, US
• Chandramouli Visweswariah · Croton-on-Hudson, US
• Michael H. Wood · Detroit, US
• Vladimir Zolotov · Putnam Valley, US

Key dates

• Filing date: Dec 6, 2011
• Grant date: Oct 15, 2013
• Expiry date: Dec 6, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2111/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.