Integrated circuit structure having substantially planar N-P step height and methods of forming
US8563394B2 · kind B2 · utility
2Cited by
1References
15Claims
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Key dates
| Filing date | Apr 11, 2011 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Sep 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.