Reducing effects of erase disturb in a memory device
US8565018B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Oct 22, 2013 |
| Priority date | — |
| Expiry date | Jun 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.