FinFET with improved gate planarity
US8569125B2 · kind B2 · utility
11Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jan 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.