SRAM-type memory cell
US8575697B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Mar 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.